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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MRFIC1502/D The MRFIC Line Integrated GPS Downconverter This integrated circuit is intended for GPS receiver applications. The dual conversion design is implemented in Motorola's low-cost high performance MOSAIC 3 silicon bipolar process and is packaged in a low-cost surface mount TQFP-48 package. In addition to the mixers, a VCO, a PLL and a loop filter are integrated on-chip. Output IF is nominally 9.5 MHz. * 65 dB Minimum Conversion Gain * 5 Volts Operation * 50 mA Typical Current Consumption * Low-Cost, Low Profile Plastic TQFP Package * Device Marking = M1502 MRFIC1502 1.575 GHz GPS DOWNCONVERTER CASE 932-02 (TQFP-48) GND 48 GND VCO VT GND VCC5 GND VCO CE GND SF CAP1 GND 1 2 3 4 5 6 7 8 9 GND 47 GND 46 GND 45 RF IN GND VCC1 GND 44 43 42 41 TO BPF 40 FROM BPF GND 39 38 GND 37 36 35 34 33 GND 38 MHz TRAP 38 MHz TRAP BYPASS CAP IF OUT VCC2 GND TQFP-48 ACTIVE FILTER VCO 40 2 32 31 30 29 GAIN CONTROL LOOP FILTER 28 VCC3 27 GND 26 GND 25 GND 13 C2A 14 C2B 15 C1 16 CA 17 CB 18 DCX0 19 20 21 CLK OUT 22 GND 23 GND 24 GND PHASE DETECTOR SF CAP2 10 GND 11 GND 12 VCC4 GND Pin Connections and Functional Block Diagram (c) Motorola, Inc. 1997 MOTOROLA RF DEVICE DATA MRFIC1502 1 MAXIMUM RATINGS Rating DC Supply Voltage DC Supply Current Operating Ambient Temperature Storage Temperature Range Lead Soldering Temperature Range (10 seconds) Symbol VDD IDD TA Tstg -- Limit +6.0 60 - 40 to + 100 - 65 to +150 +260 Unit Vdc mA C C C ELECTRICAL CHARACTERISTICS (TA = 25C, and VCC = 5 V, Tested in Circuit shown in Figure 1 unless otherwise noted) Characteristic Supply Voltage Supply Current L-Band Gain (Measured from L-Band Input to 47 MHz Output) IF Gain (Measured from 47 MHz Input to 9.5 MHz Output with Gain Control at Maximum) Conversion Gain (Measured from L-Band Input to 9.5 MHz Output with Gain Control at Maximum) Gain Control (Externally Adjustable 0 to 5.0 V, Maximum at 0 V) Noise Figure (Double Sideband) L-Band Input VSWR (Measured into 50 ; 1575.42 5.0 MHz) First IF Output VSWR (Measured into 50 ; 47.74 5.0 MHz) Second IF Output VSWR (Measured into 50 ; 9.5 5.0 MHz) Input Impedance @ 1st IF 47.7 5 MHz (For Reference Only) Output 1.0 dB Compression Point First LO (Measured at the First IF Output) All Other Harmonics (Measured at the First IF Output) 38.1915 MHz Leakage at First IF Output Second LO (Measured at the Second IF Output) All Other Harmonics (Measured at Second IF Output) Reference Oscillator Input Clock Output Frequency Amplitude Low HIgh (Clock Amplitude Measured with the Output Loaded in 15 pF and 40 k) Duty Cycle VCO Lock Voltage Phase Detector Gain VCO Modulation Sensitivity Min 4.75 -- -- -- 65 -- -- -- -- -- -- -- -- -- -- -- -- 400 2Xfref Typ -- -- 20 45 -- 40 9.5 2:1 2:1 2:1 2000 -7 -20 -45 -50 -25 -45 -- -- Max 5.25 60 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4500 2Xfref Unit Vdc mA dB dB dB dB dB -- -- -- dBm dBm dBm dBm dBm dBm mVpp -- 2.0 45 1.2 -- -- -- 0.16 15 0.8 -- 55 3.0 -- -- V V % V V/Radian MHz/V MRFIC1502 2 MOTOROLA RF DEVICE DATA L7 C22 C21 L6 VCC RF INPUT L10 C19 C18 48 1 CR1 L3 C17 2 R1 VCC L1 C15 4 C16 5 6 C35 7 8 C3 9 10 C2 11 12 13 14 15 C5 C4 16 C6 17 C7 18 C1 C36 L1 DXCO VCC CLOCK OUTPUT 68 pF, ATC 0.4 pF, ATC 2.7 pF, MA45233-123, MACOM 2.2 H, 1008CS-222XKBC, COILCRAFT 2.2 nH, LL2012-F2N2S, TOKO 2.2 H 220 nH 0.56 H 0.27 H 10 k 220 C37 19 20 21 22 23 24 26 25 LOOP FILTER ACTIVE FILTER VCO 33 C12 C36 32 IF OUTPUT 31 C10 30 29 28 C8 27 C9 GAIN CONTROL VCC L4 C11 VCC L5 C13 3 35 C14 C31 34 47 46 45 44 43 42 41 40 39 38 37 36 L9 C34 C23 L8 R3 C24 C20 TQFP-48 40 2 PHASE DETECTOR C1, C8, C10, C12, C13, C15, C19, C20, C37 C4, C5 C6, C7, C31 C2, C3 C14 C16, C18, C36 C17 C21 C9, C11, C34, C36 C22, C23 10,000 pF 5600 pF 1000 pF 1.0 F 3.9 pF, ATC 27 pF, ATC 15 pF, ATC 5.6 pF, ATC 47 pF, ATC 120 pF, ATC C24 C35 CR1 L1, L4, L5, L10 L3 L6 L7 L8 L9 R1 R3 Figure 1. Test Circuit Configuration MOTOROLA RF DEVICE DATA MRFIC1502 3 Table 1. Port Impedance Derived from Circuit Characterization Zin Ohms R 38.3 54.45 43 560 jX -16.09 11.3 1.5 -850 Pin Number Pi N b 44 40 39 32 Pin Name Pi N RF IN TO BPF FROM BPF IF OUT f (MHz) 1575.42 47.74 47.74 9.5 Zin represents the input impedance of the pin. APPLICATION INFORMATION Design Philosophy The MRFIC1502 design is a standard dual downconversion configuration with an integrated fixed frequency phase- locked loop to generate the two local oscillators and the buffer to generate the sampling clock for a digital correlator and decimator. The active device for the L-band VCO is also integrated on the chip. This chip is designed in the third generation of Motorola's Oxide Self Aligned Integrated Circuits (MOSAIC 3) silicon bipolar process. Circuit Considerations The RF input to the MRFIC1502 is internally matched to 50 ohms. Therefore, only AC coupling is required on the input. The output of the amplifier is fed directly into the first mixer. This mixer is an active Gilbert Cell configuration. The output of the mixer is brought off-chip for filtering of the unwanted mixer products. The amplifier and mixer have their own VCC supply (pin 42) in order to reduce the amount of coupling to the other circuits. There are two bypass capacitors on this pin, one for the high frequency components and one for the lower frequency components. These two capacitors should be placed physically as close to the bias pin as possible to reduce the inductance in the path. The capacitors should also be grounded as close to the ground of the IC as possible, preferably through a ground plane. The output impedance of the first mixer is 50 ohms, while the input impedance to the first IF amplifier is 1 k. There is a trap (zero) designed in at the second LO frequency to limit the amount of LO leakage into the high gain first IF amplifier. The first IF amplifier is a variable gain amplifier with 25 dB of gain and 40 dB of gain control. The gain control pin can be grounded to provide the maximum gain out of the amplifier. If the baseband design utilizes a multi-bit A/D converter in the digital signal processing chip, this amplifier could be used to control the input to the A/D converter. The amplifier has an external bypassing capacitor. This capacitor should be on the order of 0.01 F, and again should be located near the package pin. The second mixer design is also a Gilbert Cell configuration. The interface between the mixer and the second IF amplifier is differential in order to increase noise immunity. This differential interface is also brought off-chip so that some additional filtering could be added in parallel between the output of the mixer and input to the amplifier. This filtering is primarily to reduce the amount of LO leakage into the final IF amplifier and is achieved using a single 3.9 pF capacitor across the differential ports. The value of the capacitor determines the high frequency of the low pass structure. The supply pin for the IF circuits is pin 33. This supply pin should be isolated from the other chip supplies in order to reduce the amount of coupling. The recommended capacitors are a 47 pF and a 0.01 F, in parallel to bypass the supply to ground and should be placed physically as close to the pin as possible. The output of the second IF amplifier is 50 ohms with a bandwidth of 5.0 MHz. This signal must be filtered before being digitized in order to limit the noise entering the A/D converter. VCO Resonator Design The design and layout of the circuits around the voltage controlled oscillator (VCO) are the most sensitive of the entire layout. The active device and biasing resistors are integrated on the MRFIC1502. The external circuits consist of the power supply decoupling, the capacitors for the integrated supply superfilter, the resonator and frequency adjusting elements, and the bypassing capacitor on the emitter of the active device. The VCO supply is isolated from the rest of the PLL circuits in order to reduce the amount of noise that could cause frequency/phase noise in the VCO. The supply should be filtered using a 22 H inductor in series and a 27 pF and 0.01 F in parallel. The 27 pF capacitor should be series resonant at least as high as the VCO frequency to get the most L-band bypassing as possible. The on-chip supply filter requires two capacitors off-chip to filter the supply. The capacitors on the input (pin 8) and output (pin 10) of the filter are 1.0 F, and the output also has a high frequency bypass capacitor in parallel. The input capacitor should not be smaller than a 1.0 F to insure stability of the supply filter. The VCO design is a standard negative resistance cell with a buffer amplifier. The resonating structure is connected to the base of the active device and consists of a coupling capacitor, a hyper-abrupt varactor diode, and a wire wound chip inductor. With the values shown on the application MRFIC1502 4 MOTOROLA RF DEVICE DATA circuit, the VCO is centered at 1527.7 MHz, and the gain of the VCO is approximately 20 MHz/Volt. The above performance is heavily dependent on the capacitive structure that is used as the emitter bypass on pin 6. The total capacitance should be approximately 1.0 pF; that can be achieved using either a discrete element or a microstrip open circuited stub. The evaluation circuit shown uses a 0.4 pF capacitor. Phase-locked Loop Design The VCO signal at 1527.68 MHz is divided by 40 to get the second LO frequency of 38.19 MHz. In addition to providing the LO to the second mixer, the 38 MHz signal is output through a translator and is used as the sampling clock for the digital correlator and decimator circuits. There is an additional divide by two so the signal used by the phase detector is at 19.096 MHz. The reference input to the phase detector (pin 18) has an input sensitivity of 400 mVpp minimum and 2.5 Vpp maximum. The loop filter design is the standard op-amp loop filter, resulting in a type 2 second order loop. The layout of the discrete components around the loop filter and VCO is very critical to the performance of the phase-locked loop. Care should be taken in routing the VCO control voltage line from the output of the loop filter to the varactor diode. The output of the divide by 40 is buffered by a clock translator that converts the low level sine wave into a TTL level square wave. The loading on the buffer is high so the peak currents can reach as high as 50 mA with the maximum load of 1.0 k in parallel with 40 pF on the output. Therefore, the translator has a dedicated VCC supply, pin 28, which requires external bypassing and isolation. The recommended bypassing uses two capacitors in parallel, a 47 pF and a 0.01 F capacitor. Conclusion The MRFIC1502 offers a highly integrated downconverter solution for GPS receivers. For more detailed applications information on GPS system design refer to application note AN1610, "Using Motorola's MRFIC1502 in Global Positioning System Receivers." MOTOROLA RF DEVICE DATA MRFIC1502 5 PACKAGE DIMENSIONS 4X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350 (0.014). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BASIC 0.050 0.150 0.090 0.200 0.500 0.700 12 _REF 0.090 0.160 0.250 BASIC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.007 0.011 0.053 0.057 0.007 0.009 0.020 BASIC 0.002 0.006 0.004 0.008 0.020 0.028 12 _REF 0.004 0.006 0.010 BASIC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF 0.200 (0.008) AB T-U Z 9 A1 48 37 A DETAIL Y P 1 36 -T- B B1 12 25 -U- V AE V1 AE 13 24 -Z- S1 -T-, -U-, -Z- S 4X DETAIL Y 0.200 (0.008) AC T-U Z G -AB- -AC- AD BASE METAL 0.080 (0.003) AC DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X M_ TOP & BOTTOM R GAUGE PLANE 0.080 (0.003) SECTION AE-AE MRFIC1502 6 EEE CCCC EEE CEEE CCC CCCC F D M N J C E 0.250 (0.010) AC T-U S Z S H DETAIL AD W K X Q_ CASE 932-02 ISSUE D MOTOROLA RF DEVICE DATA Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://www.motorola.com/sps/ JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA RF DEVICE DATA MRFIC1502 7 MRFIC1502/D |
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